AMCC 405GPr

	v. 4.1
Architecture:	PowerPC
Processor group:	PowerPC 405
Markets:	storage, telecommunications
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The AMCC PowerPC® 405GPr 32-bit RISC processor is designed to provide a flexible, fast time-to-market hardware solution to satisfy the demands of high-performance embedded applications. Implemented in the scalable PowerPC architecture, the 405GPr processor maintains code compatibility with other PowerPC processors for ease in migration and faster time-to-market. An optimized balance of performance, low power, and features makes it an ideal solution for communication, data storage, and pervasive computing applications.

The 405GPr processor supports speeds of up to 400MHz. It incorporates a rich mix of features, such as a PCI interface, an SDRAM Controller, a 64-bit on-chip CoreConnect bus, Ethernet and other on-chip peripheral support, and the CodePack code compression engine. In addition, power management features, a small form factor, and low power consumption make the AMCC 405 processor family an ideal platform for applications ranging from networking to video.

PowerPC 405GPr embedded cores incorporate features to enable high performance without increasing chip size or power. A 4-KB on-chip SRAM stores critical code and data.

A five-stage pipeline increases throughput and enables speeds of up to 400MHz. It includes a fetch, decode, execute, write-back, and load writeback stage.

The single-issue execution unit is especially useful in switching and routing equipment where real-time operation is critical. The unit, which contains the register file, arithmetic logic unit (ALU) and the multiply-accumulate (MAC) unit, performs all integer instructions in hardware. The register file, comprised of thirty-two 32-bit general purpose registers (GPR), enables either a load or a store operation to execute in parallel with an ALU operation.

The memory management unit (MMU) provides address translation, flexible memory protection, and storage-attribute control. It supports multiple page sizes as well as a variety of storage-protection attributes and access-control options. Multiple page sizes improve memory efficiency and minimize the number of buffer misses.

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